Những gì chúng tôi có thể cung cấp
- Working in a fast paced, flexible, and multinational working environment.Working from Mondays to Fridays.
- Chance to travel onsite (in 49 countries).
- 18 paid leaves per year (including 12 annual leaves 6 personal leaves).100% full salary in probation period.
- Medical Benefit (Personal) and Family based on levels.
- Internal Training (Technical & Functional). Scope of English Training.
- Insurance plan based on full salary 13th salary Performance Bonus.
Mô tả công việc
Navigos Search's Client is a global technology organization with a strong international presence across 60 countries and over 220,000 employees worldwide. This company partners with some of the world’s leading enterprises across key industries including finance, healthcare, manufacturing, telecommunications, and more. With a mission to drive innovation through cutting-edge engineering, digital transformation, and cloud services, this is a great opportunity to grow your career in a dynamic, multicultural environment.
We are looking for RTL Engineers who:
- Work on Register Transfer Level (RTL) design using Verilog for digital circuits and embedded systems.
- Translate functional requirements into detailed micro-architectural designs.
- Apply a solid grasp of digital design fundamentals, such as combinational/sequential logic and finite state machines.
- Ensure compliance and implementation using industry-standard bus protocols (e.g., AMBA: AHB, AXI, APB).
- Support the development and integration of Built-In Self-Test (BIST) features.
- Troubleshoot and resolve issues in digital logic design through simulation and debugging.
- Collaborate with cross-functional teams to deliver robust and reliable design components.
- Create and enhance testbenches and simulation environments for design verification.
- Optionally use scripting languages (Perl, Python, Tcl) for automation and productivity improvements.
Yêu cầu
- Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or a related technical discipline.
- Minimum of 3 years of professional experience in RTL design using Verilog.
- Strong analytical skills with the ability to identify an