DFT Manager (Full chip/ IP)

Role Summary
Lead and mentor a team of DFT engineers through full-chip/IP DFT and test vector generation to ensure delivery of DFT architecture and implementation, including silicon validation and issue resolution
Key Responsibilities

Lead and manage a team of DFT engineers to execute DFT plans, including assigning tasks, setting goals, and providing guidance and training.
Define and implement DFT methodologies and strategies across SoC functions, including scan, BIST, ATPG, compression, SSN, IP testing and so on.
Develop approaches that reduce test cost, enhance product quality, and improve yield in advanced process technologies.
Oversee the DFT flow from architecture through to silicon validation, including pattern generation, coverage analysis, and debug in RTL/gate-level simulations. Interface with test engineers for ATPG/MBIST delivery.
Engage closely with RTL, physical design, verification, and manufacturing teams to integrate DFT features and carry out ship-ready transitions.
Communicate DFT status, risks, and technical bottlenecks to senior management and customers; recommend actionable solutions.